AVL Synchronization and TLM

AVL provides a simple and flexible synchronization mechanism, similar to the UVM TLM.

The mechansim is based on the following classes:

avl_list

Inheritance diagram of avl._core.list

The avl.List is extended from the Python List variable and as such all methods familiar to Python users are available.

The avl.List provides adds the List.blocking_pop method and the alias List.blocking_get method to wait on an item being available in the list.

async def run_phase(self):
while True:
    item = await self.seq_item_port.blocking_get()
    self.info(f'New Item: {item}')

avl_fifo

Inheritance diagram of avl._core.fifo

The avl.Fifo is extended from avl.List and provides a FIFO queue.

When attempting to append, extend or insert the method will block until there is space in the FIFO.

avl_port

Inheritance diagram of avl._core.port

The avl.Port is equivalent the the UVM port class, but also serves as the TLM port in sequencers.

Effectively the avl.Port provides the one-to-many communication mechanism between components.