AVL Methodology

AVL follows the UVM methodology for verification, but as the intention of AVL is to simplify the verification process, the implementation does not enforce a specific flow.

Connecting Sequencers and Drivers

The variety of ports has been simplified from UVM.

A single avl.Port is provides. This implements one-to-many data transfer to each of its connections.

It is recommended to connect an avl.Port to an avl.List as this provides the blocking mechanism for the consumer.

As the done and response handshaking is built into the avl.SequenceItem class, the sequencer does not need to implement magic functions to synchronise with the driver.

async def connect_phase(self):
    self.sequencer.seq_item_export.connect(self.driver.seq_item_port)